Multiple alternate configurations for an integrated circuit device

ABSTRACT

A method of configuring an integrated circuit device to perform a function includes storing a plurality of configurations for performing the function, each of the configurations being designed for a different characteristic of a particular input to the function. Inputs are received for the function, including the particular input. The characteristic of the particular input as received is examined, and one of the plurality of configurations is instantiated based on that characteristic of the particular input as received. A machine-readable data storage medium may be encoded with instructions to perform the method. A programmable device may be configured according to the method, and also may be incorporated into a heterogeneous system.

FIELD OF THE INVENTION

This invention relates to the preparation of multiple alternateconfigurations for an integrated circuit device, and particularly for aprogrammable integrated circuit device such as a field-programmable gatearray (FPGA) or other type of programmable logic device (PLD). Moreparticularly, this invention relates to preparing such configurationsfor a programmable integrated circuit device in a larger heterogeneoussystems.

BACKGROUND OF THE INVENTION

Early programmable devices were one-time configurable. For example,configuration may have been achieved by “blowing”—i.e., opening—fusiblelinks. Alternatively, the configuration may have been stored in aprogrammable read-only memory. Those devices generally provided the userwith the ability to configure the devices for “sum-of-products” (or“P-TERM”) logic operations. Later, such programmable logic devicesincorporating erasable programmable read-only memory (EPROM) forconfiguration became available, allowing the devices to be reconfigured.

Still later, programmable devices incorporating static random accessmemory (SRAM) elements for configuration became available. Thesedevices, which also can be reconfigured, store their configuration in anonvolatile memory such as an EPROM, from which the configuration isloaded into the SRAM elements when the device is powered up. Thesedevices generally provide the user with the ability to configure thedevices for look-up-table-type logic operations.

At some point, such devices began to be provided with embedded blocks ofrandom access memory that could be configured by the user to act asrandom access memory, read-only memory, or logic (such as P-TERM logic).Moreover, as programmable devices have become larger, it has become morecommon to add dedicated circuits on the programmable devices for variouscommonly-used functions. Such dedicated circuits could includephase-locked loops or delay-locked loops for clock generation, as wellas various circuits for various mathematical operations such as additionor multiplication. This spares users from having to create equivalentcircuits by configuring the available general-purpose programmablelogic.

While it may have been possible to configure the earliest programmablelogic devices manually, simply by determining mentally where variouselements should be laid out, it was common even in connection with suchearlier devices to provide programming software that allowed a user tolay out logic as desired and then translate that logic into aconfiguration for the programmable device. With current larger devices,including those with the aforementioned dedicated circuitry, it would beimpractical to attempt to lay out the logic without such software. Suchsoftware also now commonly includes pre-defined functions, commonlyreferred to as “cores,” for configuring certain commonly-usedstructures, and particularly for configuring circuits for mathematicaloperations incorporating the aforementioned dedicated circuits. Forexample, cores may be provided for various trigonometric or algebraicfunctions.

Available programming software has heretofore assumed that when a userspecifies a certain logic design, that design is static. However, insome cases, it may be that the design includes a function that isparameterizable or that may operate differently when its inputs are indifferent ranges. This is particularly the case where the programmabledevice is part of a larger heterogeneous system where some other device,such as a microprocessor, calls upon the programmable device to processdata. Depending on the characteristics of those data, slightly differentversions of the user logic design may be required.

SUMMARY OF THE INVENTION

A programming method and software may be provided that can accommodateuser logic designs that may call for different configurations fordifferent possible user data to be processed. One type of such a designmay be used when the function to be programmed or configured may beparameterizable. Another type of such a design may be used when thefunction to be programmed or configured may operate differently fordifferent ranges of input data.

According to such a method, a “library” of different hardwareconfigurations may be created for each of those functions in a userlogic design that may operate differently for different parameters ordata ranges, so that a more efficient configuration can be instantiatedat runtime when the input parameters and data are known. Although thisprocess may be characterized loosely as being “speculative,” in thatconfigurations are created that may never, or rarely, be used, any“speculative” behavior may be intelligent or educated.

For example, the user may be asked to provide an expected range ofvalues of the expected input data for the function to be implemented, orthe expected sets of parameters if the function is parameterizable.Thus, the process usually would not involve haphazard guesswork inselecting the various configurations to be created.

The process may also include the creation, along with the variousconfigurations based on the expected inputs, of a generic configurationthat can handle a full range of possible inputs. However, such aconfiguration normally can be expected to consume larger amounts ofdevice resources, and therefore would be expected to be selected atruntime only in a small portion of cases, if the other members of thelibrary of “speculative” configurations were properly selected.

The creation of a heterogeneous system as described above, including thelibrary of speculative configurations, as well as the specification ofwhich members of the library should be instantiated in a particularruntime situation, can advantageously be carried out using a high-levelprogramming language, rather than a hardware description language. Onehigh-level programming language that may be adopted for specifyingcircuitry of an integrated circuit device, such as for configuring aprogrammable device, is OpenCL (Open Computing Language), although useof other high-level languages, and particularly other high-levelsynthesis languages, including OpenMP (Open Multi-Processing), OpenACC(Open Accelerator) C, C++, Fortran, C#, F#, BlueSpec and Matlab, also iswithin the scope of this invention. Nevertheless, the present inventionis not limited to high-level programming languages.

In accordance with the present invention there is provided a method ofconfiguring an integrated circuit device to perform a function. Themethod includes storing a plurality of configurations for performing thefunction, each of the configurations being designed for a differentcharacteristic of a particular input to the function. Inputs arereceived for the function, including the particular input. Thecharacteristic of the particular input as received is examined, and oneof the plurality of configurations is instantiated based on thatcharacteristic of the particular input as received.

A machine-readable data storage medium encoded with instructions toperform the method also is provided, as is a programmable deviceconfigured according to the method, as well as a system incorporatingsuch a device.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features of the invention, its nature and various advantageswill be apparent upon consideration of the following detaileddescription, taken in conjunction with the accompanying drawings, inwhich like reference characters refer to like parts throughout, and inwhich:

FIG. 1 shows a heterogeneous system with which the present invention maybe used;

FIG. 2 shows an example of a function block that may be configured in aprogrammable device;

FIG. 3 shows a particular implementation of the function block of FIG. 2for a known parameter;

FIG. 4 shows a particular implementation of the function block of FIG. 2for an arbitrary parameter;

FIG. 5 shows three alternative implementations of the function block ofFIG. 2 for different parameters;

FIG. 6 shows a control flow graph of at least a portion of a function tobe implemented in another example of a function block that may beconfigured in a programmable device;

FIG. 7 shows an example of a function block, similar to that of FIG. 2,for implementing a floating-point arithmetic function;

FIG. 8 shows two alternative implementations of the function block ofFIG. 7 for different parameters;

FIG. 9 shows a flow diagram of an example of a method in accordance withembodiments of the present invention;

FIG. 10 is a cross-sectional view of a magnetic data storage mediumencoded with a set of machine-executable instructions for performing themethod according to the present invention;

FIG. 11 is a cross-sectional view of an optically readable data storagemedium encoded with a set of machine executable instructions forperforming the method according to the present invention; and

FIG. 12 is a simplified block diagram of an illustrative systememploying a programmable logic device incorporating the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

Synthesis of software code for an FPGA or similar programmable deviceinvolves transforming a software function into a hardware circuit. In aheterogeneous system, an FPGA may be used to provide hardwareacceleration for certain functions that are less efficiently performedby a microprocessor. Thus, in such a system, the microprocessor willpass the function to the FPGA or other programmable device while itperforms other functions for which it is better suited. The functionpassed to the programmable device may be parameterized, and the mostefficient circuit to perform that function may differ depending on theparameters. Similarly, the function passed to the programmable devicemay be simpler for certain ranges of inputs and more complex for otherranges of inputs, so the most efficient circuit to perform that functionmay differ depending on the range of the input data.

When configuring a programmable device in such a system to perform sucha function, one solution could be to configure the function in its mostgeneric form, so that it can execute regardless of the parameters or therange of values. However, that may result in an unnecessarily largecircuit configuration, consuming more device area than necessary andoperating more slowly than might be possible if a smaller configurationcould be instantiated.

By the time the rest of the heterogeneous system needs the programmabledevice to perform a particular function, the nature of the function tobe performed is more well-defined. Thus, the parameters (if the functionis parameterized) and the data values are known. However, one cannotwait until that moment to compile the programmable device configuration.Thus, in accordance with embodiments of the present invention, variousconfigurations of the function to be performed are compiled in advance,and the correct one of those configurations, based on the parametersand/or the data, is instantiated in the programmable device at runtime.

The determination of which configurations to compile in advance may beassisted by accepting input from the user, at the time the system to becompiled is specified to the programming software, which specifies thelikely different sets of parameters and/or ranges of data values thatcan be expected at runtime. In some cases, the user may be able tospecify with certainty that only certain configurations will be needed.In other cases, the user may be able to specify ranges of inputs withsufficient certainty for the system to select specific configurationsthat may be needed. In still other cases, it may not be possible tolimit the number of configurations with certainty, and in those cases,along with the specified configurations, a generic configuration alsomay be compiled, and indeed, the generic configuration may be compiledin most cases.

The precompilation of the possible configurations may allow theselection of the programmable device hardware to be included in theheterogeneous system to be limited to a device size that will supportthe largest precompiled configuration. Even in a case whereprecompilation of a generic configuration is still needed, it may bepossible, if more than one programmable device is included in theheterogeneous system, to provide a mix of larger and smallerprogrammable devices, rather than providing all of the programmabledevices in the largest size that might be expected to be needed.

Embodiments of the invention will now be described with reference toFIGS. 1-9.

FIG. 1 shows an example of a heterogeneous system 100, which includesone or more microprocessors 101, one or more graphics processing units102, one or more digital signal processing units 103, one or more FPGAs104 (or similar programmable devices), and one or more memory units 105,all interconnected by an interconnection network or bus 106. System 100may be constructed as a set of interconnected discrete components, or asan SoC or “system-on-chip” on a single integrated circuit device.

As is known, each component in heterogeneous system 100 may beparticularly well suited to a different function. For example,microprocessor 101 may be best suited for general-purpose irregularcontrol applications, graphics processing units 102 may be best suitedfor floating-point vector computations on large datasets, digital signalprocessing units 103 may be best suited for highly flexible signalprocessing algorithms, while FPGAs 104 may be best suited forhigh-performance datapath and control functions.

Thus, there may be times during operation of system 100 that amicroprocessor 101 would have to call on an FPGA 104 to perform afunction. When system 101 is constructed, it may be known that that typeof function will be required, but the particulars are not known, andtherefore multiple configurations of the function will be precompiled asdiscussed above.

For example, if a Finite Impulse Response (FIR) filter will be required,that FIR filter function may be passed to FPGA 104 by microprocessor101, in a high-level language (such as OpenCL), with three parameters,representing an input address “in”, an output address “out”, and thenumber of taps, n, in the filter:

-   -   int main( . . . ) {        -   #pragma accel fpga        -   fir(in,out,n);        -   . . .            -   return 0;    -   }

Using known techniques, the function would be implemented as shown inFIG. 2. FIR filter function block 200 includes a functional core 201, aswell as a bank 202 of control registers. Registers 212, 222, 232 wouldreceive the three parameters through control port 203. Register 212would receive the input address which tells core 201 where in memory 204to find the input data. Register 222 would receive the output addresswhich tells core 201 where in memory 204 to write the output data.Register 232 would receive the variable indicating the number of tapsrequired in the filter to be implemented in core 201. Later, a ‘1’ wouldbe written to “Go” register 242 to tell the filter to begin processingdata, and when the filter would finish, it would write a ‘1’ to “Done”register 252.

For FIR filter function block 200 to work, functional core 201 wouldhave to capable of operating at the maximum possible number of expectedtaps, n. If that maximum possible number occurs in only a small fractionof cases, then providing a functional core 201 to account for themaximum possible number results in an inefficient circuit.

For a constant, relatively small number of taps, n—e.g., 8 taps—one cancompile a very efficient circuit such as circuit 300 of FIG. 3. At theother extreme would be circuit 400 of FIG. 4, which can accommodate anarbitrary number of taps, n, subject to limitations of availablememories 401, and requiring complex counter-and-control-logic circuitry402. Circuit 400 is not only less efficient than circuit 300—e.g., interms of device area—but it also may execute more slowly, even for thesame number of taps.

However, in accordance with embodiments of the invention, rather thancompiling a single arbitrarily-sized FIR filter circuit, one can compilea number of FIR filter circuits designed for different numbers of taps.For example, if the number of taps can be 4 or 8, two different FIRfilter circuits can be compiled—one 4-tap filter and one 8-tapfilter—and the correct bitstream (i.e., to instantiate a 4-tap filter oran 8-tap filter) can be loaded by microprocessor 101 to instantiate theneeded circuit. Even if there remained the possibility of other numbersof taps, so that an arbitrarily-sized FIR filter circuit also had to becompiled, that bitstream would not be loaded unless that case occurred,so there would be no waste of device resources for the smaller filtersthat were individually compiled. The various precompiled circuits orconfigurations can be stored in a memory 105 of heterogeneous system100, or in a memory 140 within FPGA 104 (see FIG. 13)

In such a case, the function, set forth above, that would be passed frommicroprocessor 101 to FPGA 104 would be transformed, in a high-levellanguage (such as OpenCL), to:

-   -   int main( . . . ) {        -   . . .            -   // Reprogram FPGA            -   if (N==4) {                -   download_fpga_bitstream(fir.4.bitstream);            -   } else if (N==8) {                -   download_fpga_bitstream(fir.8.bitstream);            -   } else {                -   download_fpga_bitstream(fir.N.bitstream);            -   }            -   // Set parameters            -   io_write(FIR_CONTROL_PORT+0, &in[0]);            -   io_write(FIR_CONTROL_PORT+1, &out[0]);            -   io_write(FIR_CONTROL_PORT+2, n);            -   // Set Go bit

The result of that function would be to instantiate one of the threeblocks shown in FIG. 5. If N=4, fir.4.bitstream 501 would be downloaded,resulting in instantiation of a FIR function block 500 designed for N=4.If N=8, fir.4.bitstream 511 would be downloaded, resulting ininstantiation of a FIR function block 510 designed for N=8. If the valueof N were anything other than 4 or 8, fir.N.bitstream 521 would bedownloaded, resulting in instantiation of a FIR function block 520 forarbitrary N (one would normally endeavor to create the most efficientpossible such block).

More generally, in a heterogeneous system, which may use a high-levellanguage such as OpenCL, when microprocessor 101 requires a functionthat is more efficiently performed in FPGA 104, it can call FPGA 104 asan accelerator to perform the function. Microprocessor 101 couldconfigure an unconfigured FPGA 104 with the function, but that may betoo time-consuming. Therefore, FPGA 104 may initially be at least partlyconfigured with a version of the function, and microprocessor 101 wouldthen reconfigure, or partially reconfigure, FPGA 104 with the desiredversion of the function.

A number of techniques may be used to determine which possible“speculative” functions to create.

For example, one technique to determine which possible “speculative”functions to create would be to examine the flow control graphs (seeflow control graph 600 in FIG. 6) of the processes to be run byheterogeneous system 100, with each branch decision resulting in two“speculative” functions to be compiled—one function 602 for when thebranch condition 601 is ‘true’ and one function 603 for when the branchcondition 601 is ‘false’. To reduce the number of functions required,branch conversion, as described in copending, commonly-assigned U.S.patent application Ser. No. 13/923,975, filed Jun. 21, 2013, which ishereby incorporated by reference herein in its entirety, could be used.

Another example of a technique to determine which possible “speculative”functions to create would be to examine loop bounds in the processes tobe run by heterogeneous system 100. For example, if a loop bound is avariable, rather than a constant (e.g., “for i=1 to x), the loop can beunrolled, creating versions for different values of x up to somereasonable number. An arbitrary version (not unrolled) for larger xwould likely also be created, unless the maximum value of x were knownto be limited.

For certain types of functions, the expected range of input values mightbe used to determine which “speculative” functions to create.Floating-point arithmetic functions consume significant resources. Forexample, in an FPGA, a floating-point adder may consume about 21 timesthe amount of resources as an integer or fixed-point adder. However, forcertain input values, fixed-point operations or range-reduced operationsmay produce results of equivalent accuracy to the floating-pointoperation. Therefore, if the expected input values for a floating-pointoperation are known, it may be possible to configure instead afixed-point operation designed for those input values to provide as gooda result, at less cost, than the original floating-point operation.

Therefore, in accordance with other embodiments of the invention, for afloating-point operation to be configured, two additional variables maybe introduced, representing the upper and lower bounds of the expectedinput to the floating-point operation. These could be specified by theuser, or deduced from the nature of the operation, or, duringcompilation, any floating-point operation could be identified by thecompiler which could then ask the user to provide the upper and lowerbounds of the input. The floating-point operation could then beimplemented as a suitably designed fixed-point operation. This techniquemay be referred to as “value profiling.”

A function block 700 that could be compiled for such an operation isshown in FIG. 7, and is similar to FIR filter function block 200 of FIG.2. Function block 700 includes a functional core 701, as well as a bank702 of control registers. Registers 712, 722 would receive the twoparameters Param1 and Param2 indicating the range of expected inputvalues through control port 703. Later, a ‘1’ would be written to “Go”register 742 to tell functional core 702 to begin processing data, andwhen functional core 702 would finish, it would write a ‘1’ to “Done”register 752. In this case, register 732 would function as an errorregister. A flag (e.g., a ‘1’) could be written to register 732 in theevent that an input value were received that was outside the boundsdefined by Param1 and Param2. Microprocessor 101 would thus be alertedthat it had to do something different.

One option for microprocessor 101 in such a case would be to fall backto a less-efficient configuration for the full floating-point version ofthe function, which could be compiled “speculatively” along with themore efficiently designed fixed-point version. In such a case, thefunction, set forth above, that would be passed from microprocessor 101to FPGA 104 would be transformed, in a high-level language (such asOpenCL), to:

-   -   int main( . . . ) {        -   . . .            -   // Reprogram FPGA            -   download_fpga_bitstream(f.FIXED.bitstream);            -   // Set parameters            -   . . .            -   // Set Go bit            -   . . .            -   // Wait for HW to finish            -   . . .            -   // Check for Value Range Error            -   if (io_read(FIR_CONTROL_PORT+2)==1) {                -   // Rerun with FLOATING POINT impl                -   download_fpga_bitstream(f.FLOATING.bitstream);                -   // Set parameters            -   }

The result of that function would be to instantiate one of the twoblocks shown in FIG. 8. First, f.FIXED.bistream 801 would be loaded intothe programmable device, resulting in instantiation of a fixed-pointfunction block 800 designed for the range of values that was provided.If during operation of block 800 an input is encountered outside thatrange, an error flag (e.g., a ‘1’) would be set in register 732. Thiswould signal to microprocessor 101 that f.FLOAT.bistream 811 would beloaded into the programmable device, resulting in instantiation of afloating-point function block 810 capable of handling arbitrary inputs(one would normally endeavor to create the most efficient possible suchblock).

In another variant (not shown) of value profiling, the system might haveprecompiled one or more additional fixed-point blocks designed fordifferent ranges of inputs outside the range specified based on userinputs, and before loading the full floating-point block, one might trythose one or more fixed-point block, in order, until no error signal isgenerated or until the full floating-point block is reached.

In still another variant (not shown) of value profiling, the systemmight have precompiled one or more additional fixed-point blocksdesigned for different ranges of inputs outside the range specifiedbased on user inputs. However, instead of providing a purely binary(i.e., ‘0’ or ‘1’ only) error signal in register 732 that indicates thatthe input values are either in or out of the specified range, a moregranular, multi-bit error signal could be provided that specifies whichrange outside the specified range the input values fall into. That wouldallow the correct additional fixed-point block, or the fullfloating-point block, as may be required, to be selected directly uponoccurrence of the initial error, rather than having to step through eachadditional block until no error occurs.

Another form of profiling that may be used to direct “speculative”configuration is control flow profiling. Specifically, analysis of thecontrol flow that is to be converted into hardware in the programmabledevice may reveal (e.g., via simulations) that certain branches orsegments of the control flow may never actually be reached. Therefore,the primary configuration could be created without the logic thatotherwise would result from those branches or segments. As in the caseof value profiling, a configuration including the logic resulting fromthose branches or segments could also be created. That configurationwould be loaded only on occurrence of an error indicating that theomitted logic was required, while in most cases, the more efficientconfiguration omitting that logic should be used.

Although the creation of “speculative” configurations as just describedcould be carried out under the direction of a user, more likely it wouldbe carried out autonomously by a processor in the system, or in aseparate programming tool, with the user at most providing the inputsdescribed above from which the system can determine which configurationsto “speculatively” create.

FIG. 9 shows one possible embodiment 900 of a method according to thepresent invention for “speculatively” programming or configuring aprogrammable integrated circuit device. Method 900 starts at 901 and, at902, which is optional because it may have been previously performed,creates a plurality of configurations, by analyzing likelycharacteristics of inputs of functions to be programmed or configured,as described above.

Next, at 903, a plurality of configurations, created at 902 orelsewhere, are stored (e.g., in memory 105). At 904, at runtime, inputs,including a particular input of interest, are received. Characteristicsof that particular input, as received, are examined at 905. The varioustypes of characteristics that may be considered have been describedabove.

As a result of the examination at 905, at 906 one of the plurality ofconfigurations that had been stored at 903 is instantiated based on thecharacteristics of the particular input of interest. Method 900 thenends at 907.

An exemplary implementation of the current invention may be aheterogeneous system such as system 100, running OpenCL, and includingthe components shown in FIG. 1, such as one or more microprocessors 101,one or more graphics processing units 102, one or more digital signalprocessing units 103, one or more FPGAs 104 (or similar programmabledevices), and one or more memory units 105, all interconnected by aninterconnection network or bus 106. Memory units 105 may store variousconfigurations of various function accelerators that may be implementedin an FPGA 104. Those configurations may be created by a configurationtool based on specification by a user of likely inputs to the functionsto be accelerated. When system 100 is powered up, one or more FPGAs 104would be at least partially configured with the various functions. Inone embodiment, when a particular function is needed by a microprocessor101, the microprocessor will cause the relevant FPGA 104 to be partiallyreconfigured, using well-known FPGA partial reconfiguration techniques,with the correct version of the function in question. The FPGA 104 maybe reconfigured or partially reconfigured more than once as themicroprocessor 101 calls that function at different times on differentinputs.

Thus it is seen that a method for efficiently configuring a programmableintegrated circuit device with a function, where the parameters of thefunction to be configured are passed to the programmable integratedcircuit device and are not known until runtime, has been provided.

Instructions for carrying out a method according to this invention forconfiguring an integrated circuit device may be encoded on anon-transitory machine-readable memory medium (e.g., a magnetic disk, anonvolatile RAM, or an optical disk such as a CD-ROM or DVD-ROM), to beexecuted by a suitable computer or similar device to implement themethod of the invention for programming or configuring PLDs or otherdevices with a configuration described by a high-level synthesislanguage as described above. For example, a personal computer may beequipped with an interface to which a PLD can be connected, and thepersonal computer can be used by a user to program the PLD usingsuitable software tools as described above.

FIG. 10 presents a cross section of a magnetic data storage medium 1200which can be encoded with a machine executable program that can becarried out by systems such as the aforementioned personal computer, orother computer or similar device. Medium 1200 can be a floppy disketteor hard disk, or magnetic tape, having a suitable substrate 1201, whichmay be conventional, and a suitable coating 1202, which may beconventional, on one or both sides, containing magnetic domains (notvisible) whose polarity or orientation can be altered magnetically.Except in the case where it is magnetic tape, medium 1200 may also havean opening (not shown) for receiving the spindle of a disk drive orother data storage device.

The magnetic domains of coating 1202 of medium 1200 are polarized ororiented so as to encode, in manner which may be conventional, amachine-executable program, for execution by a programming system suchas a personal computer or other computer or similar system, having asocket or peripheral attachment into which the PLD to be programmed maybe inserted, to configure appropriate portions of the PLD, including itsspecialized processing blocks, if any, in accordance with the invention.

FIG. 11 shows a cross section of an optically-readable data storagemedium 1210 which also can be encoded with such a machine-executableprogram, which can be carried out by systems such as the aforementionedpersonal computer, or other computer or similar device. Medium 1210 canbe a conventional compact disk read-only memory (CD-ROM) or digitalvideo disk read-only memory (DVD-ROM) or a rewriteable medium such as aCD-R, CD-RW, DVD-R, DVD-RW, DVD+R, DVD+RW, or DVD-RAM or amagneto-optical disk which is optically readable and magneto-opticallyrewriteable. Medium 1210 preferably has a suitable substrate 1211, whichmay be conventional, and a suitable coating 1212, which may beconventional, usually on one or both sides of substrate 1211.

In the case of a CD-based or DVD-based medium, as is well known, coating1212 is reflective and is impressed with a plurality of pits 1213,arranged on one or more layers, to encode the machine-executableprogram. The arrangement of pits is read by reflecting laser light offthe surface of coating 1212. A protective coating 1214, which preferablyis substantially transparent, is provided on top of coating 1212.

In the case of magneto-optical disk, as is well known, coating 1212 hasno pits 1213, but has a plurality of magnetic domains whose polarity ororientation can be changed magnetically when heated above a certaintemperature, as by a laser (not shown). The orientation of the domainscan be read by measuring the polarization of laser light reflected fromcoating 1212. The arrangement of the domains encodes the program asdescribed above.

A PLD 104 programmed according to the present invention may be used inmany kinds of electronic devices. One possible use is in a dataprocessing system 1400 shown in FIG. 12. Data processing system 1400 mayinclude one or more of the following components: a processor 1401;memory 1402; I/O circuitry 1403; and peripheral devices 1404. Thesecomponents are coupled together by a system bus 1405 and are populatedon a circuit board 1406 which is contained in an end-user system 1407.

System 1400 can be used in a wide variety of applications, such ascomputer networking, data networking, instrumentation, video processing,digital signal processing, or any other application where the advantageof using programmable or reprogrammable logic is desirable. PLD 140 canbe used to perform a variety of different logic functions. For example,PLD 104 can be configured as a processor or controller that works incooperation with processor 1401. PLD 104 may also be used as an arbiterfor arbitrating access to a shared resources in system 1400. In yetanother example, PLD 104 can be configured as an interface betweenprocessor 1401 and one of the other components in system 1400. It shouldbe noted that system 1400 is only exemplary, and that the true scope andspirit of the invention should be indicated by the following claims.

Various technologies can be used to implement PLDs 104 as describedabove and incorporating this invention.

It will be understood that the foregoing is only illustrative of theprinciples of the invention, and that various modifications can be madeby those skilled in the art without departing from the scope and spiritof the invention. For example, the various elements of this inventioncan be provided on a PLD in any desired number and/or arrangement. Oneskilled in the art will appreciate that the present invention can bepracticed by other than the described embodiments, which are presentedfor purposes of illustration and not of limitation, and the presentinvention is limited only by the claims that follow.

What is claimed is:
 1. A method of configuring an integrated circuitdevice to perform a function, the method comprising: storing, in memoryassociated with a processor, a plurality of configurations of thefunction, each of the configurations based at least in part on adifferent value or a different range of values of an input to thefunction; receiving, at the processor, the input to the function;determining, by the processor, one or more values of the input;selecting, by the processor, a configuration of the plurality ofconfigurations to instantiate based at least in part on the one or morevalues of the input; instantiating, by the processor, the selectedconfiguration on the integrated circuit device; and using, by theintegrated circuit device, the selected configuration of the function tooperate on the input.
 2. The method of claim 1 wherein: the inputcomprises one or more parameters of the function; and the one or morevalues comprises one or more respective values of at least one of theone or more parameters.
 3. The method of claim 2, wherein the one ormore values is associated with a variable loop bound in the function,wherein the method comprises the processor unrolling the variable loopbound, wherein a set of configurations of the plurality ofconfigurations are based at least in part on different values associatedwith the unrolled variable loop bound.
 4. The method of claim 2, whereinthe one or more values is associated with a branch condition in thefunction.
 5. The method of claim 1 wherein: each of the configurationsare based at least in part on the different range of values of the inputto the function; and the one or more values comprises a range of valuesto be operated on by the function.
 6. The method of claim 1, furthercomprising creating a plurality of configurations for performing thefunction, comprising analyzing likely states of the characteristic todetermine which of the plurality of configurations to create.
 7. Themethod of claim 6, wherein one of the configurations of the plurality ofconfigurations corresponds to an arbitrary state of the characteristic.8. The method of claim 6, wherein creating the plurality ofconfigurations is performed autonomously by a processor.
 9. Anon-transitory machine readable storage medium encoded with instructionsfor performing a method of configuring an integrated circuit device toperform a function, the instructions comprising: instructions to createa plurality of configurations of the function, each of theconfigurations based at least in part on a different value or adifferent range of values of an input to the function; instructions toaccept the input to the function; instructions to determine one or morevalues of the input as received; instructions to select a configurationof the plurality of configurations to instantiate based at least in parton the one or more values of the input; instructions to instantiate theselected configuration; and instructions to use the selectedconfiguration of the function to operate on the input.
 10. Thenon-transitory machine readable storage medium of claim 9, wherein theinstructions to create the plurality of configurations for performingthe function comprise instructions to create a configurationcorresponding to an arbitrary state of the characteristic.
 11. A systemcomprising: a processor; a programmable integrated circuit device incommunication with the processor for performing a function under commandof the processor; and memory storing a plurality of configurations ofthe function, each of the configurations based at least in part on adifferent value of an input to the function; wherein the processor:sends the input to the function to the programmable integrated circuitdevice; determines a value of the input; selects a configuration of theplurality of configurations to instantiate based at least in part on thevalue of the input; and instantiates the selected configuration on theprogrammable integrated circuit device; wherein the programmableintegrated circuit device uses the selected configuration of thefunction to operate on the input.
 12. The system of claim 11 wherein:the input comprises one or more parameters of the function; and thevalue comprises a respective value of at least one of the one or moreparameters.
 13. The system of claim 12, wherein the value is associatedwith a variable loop bound in the function, wherein the method comprisesthe processor unrolling the variable loop bound; wherein a set ofconfigurations of the plurality of configurations are based at least inpart on different values for the unrolled variable loop bound.
 14. Thesystem of claim 12, wherein the value is associated with a branchcondition in the function.
 15. The system of claim 11, wherein one ofthe configurations of the plurality of configurations corresponds to anarbitrary state of the characteristic.
 16. The system of claim 11,wherein the memory is part of the programmable integrated circuitdevice.
 17. The system of claim 11, wherein the memory is separate fromthe programmable integrated circuit device.
 18. The system of claim 11,wherein the processor runs under control of a program written in OpenCL.19. The system of claim 11, wherein the plurality of configurations iscreated autonomously by the processor.
 20. The system of claim 11,wherein the plurality of configurations is created autonomously by anexternal programming tool.
 21. A programmable integrated circuit devicecomprising: programmable logic circuitry communicatively coupled to aprocessor; memory storing a plurality of configurations of theprogrammable logic circuitry for performing a function, each of theconfigurations of the plurality of configurations based at least in parton a different range of values of an input to the function; wherein theprocessor selects a configuration of the plurality of configurations toinstantiate based at least in part on a range of values of the input,the processor instantiates the selected configuration, and theprogrammable logic circuitry uses the selected configuration of thefunction to operate on the input.
 22. The programmable integratedcircuit device of claim 21 wherein: the input comprises one or moreparameters of the function; and the range of values comprises a range ofrespective values of at least one of the one or more parameters.
 23. Theprogrammable integrated circuit device of claim 22, wherein the range ofvalues is associated with a variable loop bound in the function, whereinthe method comprises the processor unrolling the variable loop bound;wherein a set of configurations of the plurality of configurations aredesigned based at least in part on different ranges of values for theunrolled variable loop bound.
 24. The programmable integrated circuitdevice of claim 22, wherein the range of values is associated with abranch condition in the function.
 25. The programmable integratedcircuit device of claim 21, wherein one of the configurations of theplurality of configurations corresponds to an arbitrary state of thecharacteristic.
 26. The programmable integrated circuit device of claim21, wherein the plurality of configurations is created autonomously byan external programming tool.